Delhi’s semiconductor policy eyes R&D, manufacturing

New Delhi: The Delhi government’s proposed semiconductor policy (2026–2031) seeks to position the national capital as a major hub for semiconductor chip design, research and development (R&D), intellectual property (IP) creation and advanced packaging, with a focus on attracting investment, creating high-value jobs and building a skilled workforce

New Delhi: The Delhi government’s proposed semiconductor policy (2026–2031) seeks to position the national capital as a major hub for semiconductor chip design, research and development (R&D), intellectual property (IP) creation and advanced packaging, with a focus on attracting investment, creating high-value jobs and building a skilled workforce.

The policy’s five-year indicative budget is ₹63–79 crore, with ₹1 crore proposed for 2026–27 as seed funding (Photo for representation)

The draft policy, seen by HT, identifies five key objectives — investment attraction, employment generation, capacity building, creation of an innovation ecosystem and development of an integrated semiconductor supply chain.

Under the first objective, the government plans to attract domestic and foreign investment into fabless chip design, semiconductor R&D and assembly, testing, marking and packaging (ATMP) and outsourced semiconductor assembly and test (OSAT) sectors.

The second objective is to create direct and indirect high-value jobs in chip design, verification, R&D and advanced packaging.

The third objective focuses on developing skilled very large-scale integration (VLSI) designers, semiconductor engineers and researchers through academic partnerships, curriculum reforms and industry-linked certification programmes. The fourth objective seeks to build an innovation ecosystem, targeting at least two commercialised indigenous chip designs, or tape-outs, every year from Delhi-based startups. The fifth objective is to create an integrated supply chain covering chip design, testing, packaging and specialised semiconductor inputs.

Delhi IT minister Pankaj Singh told HT: “We plan to bring the policy in public domain by the end of this month following Cabinet approval.”

The policy also seeks to reverse the migration of semiconductor talent by encouraging professionals and alums of institutions such as IIT Delhi, IIIT Delhi, Delhi Technological University and Netaji Subhas University of Technology to return to Delhi.

It proposes developing testing and reliability centres and promoting environmentally sustainable operations, including green water infrastructure, zero liquid discharge (ZLD) norms and electronic-waste recycling.

Given Delhi’s shortage of large industrial land and water constraints, the policy does not seek to promote large silicon wafer fabrication plants. Instead, it will focus on relatively low-footprint ATMP/OSAT and specialised compound semiconductor or sensor facilities. Such units generally require significantly less land than large fabrication plants, the draft says.

The government has proposed a 50% additional capital subsidy on capital expenditure assistance approved by the Centre under India’s semiconductor mission for eligible ATMP/OSAT and compound semiconductor projects, capped at ₹50 crore per project.

Eligible units will also get a 50% subsidy on lease rentals for five years, 100% stamp duty and registration fee exemption, and, in exceptional cases, land of up to 20 acres at a 50% concessional rate.

The policy proposes a ₹2 per unit electricity tariff subsidy and 100% electricity duty exemption for 10 years, along with a 5% annual interest subvention for seven years, capped at ₹25 crore per year per unit. Eligible ATMP/OSAT units will also receive 100% reimbursement of net State Goods and Services Tax (SGST) for up to 10 years, subject to an overall cap linked to project cost.

For fabless chip-design startups and micro, small and medium enterprises, Delhi proposes an additional 20% reimbursement of eligible design expenditure, capped at ₹15 crore per unit. Companies employing a high proportion of Delhi-based talent or graduates of premier Delhi institutions can receive an additional 5% incentive, capped at ₹5 crore.

Payroll subsidies of 30& in the first year, 25% in the second and 20% in the third year have also been proposed for eligible highly skilled employees, including VLSI engineers, chip architects and verification specialists. Design units can additionally receive a 50% lease rental subsidy for five years.

The policy proposes Centres of Excellence with institutions such as IIT Delhi and DTU, with the government bearing up to 50% of the project cost, subject to a ₹10 crore cap per centre. Standalone R&D centres will be eligible for a 25% capital subsidy, capped at ₹10 crore, while patent filing costs will be reimbursed at 75% within prescribed limits.

By 2031, the government aims to support 100-plus fabless semiconductor startups, create more than 5,000 direct and indirect jobs, mobilise over ₹500 crore in private investment and facilitate 10–15 ATMP/OSAT units. It also targets five Centres of Excellence and more than 10 full chip tape-outs from Delhi-based startups.

The policy’s five-year indicative budget is ₹63–79 crore, with ₹1 crore proposed for 2026–27 as seed funding.